IIT Guwahati develops technology to design fast, secure integrated circuits.

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Guwahati: Researchers at the Automation, Verification and Security Lab of the Indian Institute of Technology-Guwahati (IIT-G) have developed secure and reliable integrated circuits (ICs) for fast and efficient computing.

This research looks at all aspects of the automated electronics design process, such as synthesis, certification and safety, and contributes to the strengthening of the electronics manufacturing ecosystem in our country.
The results have been published in top journals and conferences of the Institute of Electrical and Electronics Engineers (IEEE).

The research team is funded by ECR (Early Career Research), CRG (Core Research Grants) and Interdisciplinary Cyber ​​Physical Systems (ICPS) Science and Technology and Intel (India) Research Fellowship.
The dissertation was written by Dr. Chandan Karfa, Associate Professor, Department of Computer Science and Engineering, IIT-G and was co-authored by his research students, Muhammad Abdul Rehman, D Sina Patti, Surajit Das, Priyanka Panigrahi and Nilotpola Sarma. Are authors

The team has collaborated with various international experts.
Highlighting the importance and need for research in the field of computational power enhancement, Dr. Krafa said, “Hardware accelerator is a promising technology for improving computational performance. In hardware acceleration, specific tasks are performed through the system’s CPU core. Can be offloaded to dedicated hardware instead of performing. For example, the visualization process can be offloaded to the graphics card, thus freeing the CPU to perform other tasks. . ”
With increasing computational demands, applications require specific processors that can outperform existing CPUs.

While multi-core processors are being used in modern times, the improvement in their computing power is insufficient.

The IIT-G team emphasizes hardware acceleration specifications, often written in high-level languages ​​such as C / C ++ and converted to hardware code (or Register − Transfer Level or Register − Transfer Level (RTL code)). High Level Synthesis (HLS).
Due to the complex communication process, HLS can introduce bugs in translation design and therefore requires strict verification measures. RTL simulators are used to correct HLS, but they are slow and complicated.

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